1. Field of the Invention
The present invention relates to an ESD protection device. More particularly, the present invention relates to an ESD protection device and a fabrication method thereof.
2. Description of Related Art
Electronic devices (e.g., integrated circuits (ICs)) tend to be impacted by electrostatic discharge (ESD) in practical environment. Usually, an ESD protection device is designed between a core circuit and a pad, so as to protect the internal circuits thereof.
Depending on different voltages generated by the ESD, the ESD can be substantially classified into Human-Body Model (HBM), Machine Model (MM), and Charge-Device Model (CDM). The voltage of the ESD is much larger than the system voltage provided in the normal condition. When the ESD occurs, the ESD current is very likely to damage the electronic device. Therefore, several ESD protection measures must be considered for the electronic device, so as to effectively isolate the ESD current to prevent the device from damage. The test of the ESD protection device includes several models, namely, PD, PS, ND, and NS models. In the PD model, a positive pulse is input on the pad, such that a system voltage trace VDD is grounded. In the ND model, a negative pulse is input on the pad, such that the system voltage trace VDD is grounded. In the PS model, the positive pulse is input on the pad, such that a ground voltage trace VSS is grounded. In the NS model, the negative pulse is input on the pad, such that the ground voltage trace VSS is grounded.
FIG. 1 is a layout cross-sectional view of the ESD protection device according to U.S. Pat. No. 6,459,127. Referring to FIG. 1, n-channel metal-oxide-semiconductor (NMOS) transistors T1 and T2 of high-voltage process use parasitic silicon-controlled rectifiers (SCR) to achieve the ESD protection. The NMOS transistors T1 and T2 and the parasitic SCRs thereof are symmetrically disposed such that the current flowing through the parasitic SCRs is uniform. The conventional ESD device may provide sufficient protection against the high voltage level of HBM, where damage caused by only the ESD events of PS and NS models can be prevented. That is to say, the conventional art cannot prevent damage caused due to the ESD events of PD and ND models.
As for the ESD of PD model and ND model, in the conventional art, the ESD current/voltage is first guided from the pad 110 to the ground voltage trace VSS through the parasitic SCR element, and the ESD current/voltage is then guided from the ground voltage trace VSS to the system voltage trace VDD through another ESD protection device (not shown) coupled between the system voltage trace VDD and the ground voltage trace VSS in the IC. Finally, the ESD current/voltage is bypassed from the IC via a power supply pin through the system voltage trace VDD. Since the ESD current/voltage is not directly guided to the system voltage trace VDD from the pad 110, the guide path of the above ESD current/voltage has large parasitic resistance and parasitic capacitance, such that the ESD current/voltage may still damage the core circuit to be protected.